It is conventional in the electronic industry to encapsulate one or more semiconductor devices in a semiconductor package. These plastic packages protect a chip from environmental and handling hazards and provide a vehicle for electrical and mechanical attachment of the chip to an intended device. The packaging of semiconductor components such as power semiconductor devices involves a number of design challenges, such as cost, heat dissipation, device protection, size, performance, and reliability among others.
Various approaches to packaging semiconductor devices have been documented in the literature as well as commercialized. Some approaches use lead frames that are stamped into the desired lead configuration on which semiconductor devices are attached and wire bonded prior to encapsulation followed by post-encapsulation lead forming, i.e., lead bending and shaping to the desired configuration. This packaging technique requires custom trimming and forming machinery and tools. These trimming and forming steps and requisite machinery along with the solder or epoxy die attachment and wire bonding, ribbon bonding or clip bonding add to production time, complexity and cost.
Many semiconductor die packages use clips instead of wires to form external connections to external terminals. Such semiconductor die packages are sometimes referred to as “wireless” packages. A typical wireless package includes a clip that is attached to a semiconductor die. Wireless packages generally have better electrical and thermal performance than packages that use wire-based electrical connections. One such approach is the so-called quad flat pack no-lead (QFN) package.
As noted above, one principal consideration in the package design is heat dissipation. With respect to QFN packages, by way of example, conventional QFN packages dissipate heat from the exposed surface of the lead frame at the bottom of the package. In addition to dissipating heat from the bottom surface of the package, it can also be desirable to dissipate heat from the upper surface of a device package to pull heat away from a circuit board on which the device is mounted. Although dual heat dissipation (i.e., from both upper and lower surface of a packaged device) can provide some dissipation advantages, manufacturing and performance challenges exist that prevent these packages from being optimally reliable and cost effective. Such challenges include exposed semiconductor die surfaces, inconsistent alignment of components, and non-standardized designs that require expensive tool modifications, to name a few.
Accordingly, new package structures and methods of assembling the same are desired.